HPAVC/HPAVC CD-ROM.iso/pc/FAQSYS18.ZIP/FAQS.DAT/CGA.TXT

Text File | 1996-01-04 | 15.2 KB | 323 lines

IBM Color Graphics Adapter (CGA)

The original CGA was built with discrete logic around an MC6845 display
 controller.

On the original CGA and some clones accessing the video memory during the
active display time caused the display controller to miss some pixels (seen as
"snow"), which is the reason many programs only accesses video memory during
vertical or horizontal retrace. This is fixed in some clones and in EGA/VGA
adapters.

Basic features:
   80x25 text modes in 16colors
   320x200 4color graphics modes
   640x200 2 color graphics mode
   TTL video interface (Red, Green, Blue and Intensity)
   16KB Video RAM and 2KB ROM for 8x8 font.


Clones:
Commodore AGA:
  Combines CGA, MDA, Hercules and Plantronics support in one chip.
Chips & Tech 82c425:
  Supports both CRT and LCD displays. Greyscale on LCD, supports two softfonts
  (up to 8x16 pixels) allowing 512 characters on screen. No Snow.
Chips & Tech 82c426:
  Same as 82c425, but also supports Sleep mode, AT&T 400 line Graphics Mode,
  Color LCDs and upto 32KB video memory.


3D4h (W): Index register.
          The value written to this register selects which of the data
          registers will be accessed at 3D5h.

3D4h index 00h (W): Horizontal Total Register
Bit 0-7  Number of characters (-1) in a scan line incl. retrace.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 01h (W): Horizontal Displayed Register
Bit 0-7  Number of characters (-1) displayed during a scan line.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 02h (W): Horizontal Sync Position Register
Bit 0-7  Number of characters displayed before Horizontal Sync pulse starts.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 03h (W): Horizontal Sync Width Register
Bit 0-7  Number of character clocks during a Horizontal Sync pulse.
Note: this register is ignored on the CT82c425/6.

3D4h index 04h (W): Vertical Total Register
Bit 0-6  Number of character rows in a frame. This is adjusted by the number
         of scanlines in a character (index 9) and the Vertical Adjust (index
         5).
Note: this register is Read/Write on the CT82c425/6.

3D4h index 05h (W): Vertical Total Adjust Register
Bit 0-3  Number of scanlines added to the Vertical Total time.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 06h (W): Vertical Displayed Register
Bit 0-6  Number of character rows displayed per frame.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 07h (W): Vertical SyncPosition Register
Bit 0-6  Number of character rows displayed before the Vertical Sync pulse
         starts.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 08h (W): Interlace Mode Register
Note: this register is ignored on the CT82c425/6 and F8680.

3D4h index 09h (W): Maximum Scan Line Register
Bit 0-3  Number of scanlines (-1) in a character row.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Ah (W): Cursor Start Register
Bit 0-4  The scanline (starting from 0) within the character where the
         cursor starts.
    5-6  Cursor Attributes:
           0,2: Cursor is blinking at the blink rate.
             1: Cursor is turned off.
             3: Cursor is blinking at half the blink rate.
         The default blink rate is 1/16 of the frame rate (8 frames on, 8
         off).
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Bh (W): Cursor End Register
Bit 0-4  The scanline (starting from 0) within the character where the
         cursor ends. If the start position (index 0Ah) is larger than this
         value, no cursor is shown.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Ch (W): Start Address High Register
Bit 0-5  The upper 6 bits of the address of the start of the display.
         The lower 8 bits are in index 0Dh.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Dh (W): Start Address Low Register
Bit 0-7  The lower 8 bits of the address of the start of the display.
         The upper 6 bits are in index 0Ch.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Eh (W): Cursor Location High Register
Bit 0-5  The upper 6 bits of the address of the start of the cursor.
         The lower 8 bits are in index 0Fh.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Fh (W): Cursor Location Low Register
Bit 0-7  The lower 8 bits of the address of the start of the cursor.
         The upper 6 bits are in index 0Eh.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 10h (W): Light Pen High Register
Bit 0-5  The upper 6 bits of the latched address of the lightpen strobe.
         The lower 8 bits are in index 11h.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 11h (W): Light Pen Low Register
Bit 0-7  The lower 8 bits of the latched address of the lightpen strobe.
         The upper 6 bits are in index 10h.
Note: this register is Read/Write on the CT82c425/6.

3D4h index D3h (R/W): Grey-level Control Register #1           (CT82c426 only)
bit 0-7  GC10-17. Parameter for the Monochrome Alternate GrayScale algorithm.
         Recommended value is 43h. Bit 3 should be 0.

3D4h index D4h (R/W): Grey-level Control Register #2           (CT82c426 only)
bit 0-7  GC20-27. Parameter for the Monochrome Alternate GrayScale algorithm.
         Recommended value is E6h. Bits 3 and 7 should be 0.

3D4h index D5h (R/W): General-Purpose Register                 (CT82c426 only)
bit   0  General Purpose I/O bit 1. Data to/from the GPIO1 pin.
      1  General Purpose I/O 1 Three State Control.
         If set the GPIO1 pin is three-stated and can be used as an input.
         If clear the pin is an output.
      2  General Purpose I/O 1 Mux Control.
         If set the GPIO1 pin is fed with the data in bit 0, if clear with the
         Display Enable bit (3DAh bit 0).
      4  General Purpose I/O bit 2. Data to/from the GPIO2 pin.
      5  General Purpose I/O 2 Three State Control.
         If set the GPIO2 pin is three-stated and can be used as an input.
         If clear the pin is an output.
      6  General Purpose I/O 2 Mux Control.
         If set the GPIO2 pin is fed with the data in bit 4, if clear with the
         ROMCS/ signal

3D4h index D6h (R/W): Sleep Register                           (CT82c426 only)
bit   0  Sleep Mode Software Enable. If a 1 is written to this bit, the 82c426
         enters sleep mode when the current display fetch completes.
         In sleep mode video memory can not be accessed and the SLEEP pin is
         driven high. If a 0 is written normal operation resumes.
      1  (R) Sleep Mode Output. Reflects the state of the SLEEP output pin.
         1 if the 82c426 is in sleep mode or if the Video Enable bit is 0.

3D4h index D7h (R/W): Panel Size Register                      (CT82c426 only)
bit 0-7  Size of the upper panel (if a two panel system) in scanlines (-1).

3D4h index D8h (R/W): Panel Configuration Register             (CT82c426 only)
bit 0-2  LCD Mode. Panel type:
           0: Single Panel, Single Drive
           1: Dual-Panel, Single Drive
           2: Dual-Panel, Dual Drive
           3: Single Panel, 12bit color
           4: Single Panel, 4bit color
      3  Alternate FLM. If clear the FLM (First Line Marker) is generated as
         in the 82c425: Rising before the LP of the first line and falling
         after it. If set FLM rises when the last LP of the frame falls, and
         falls with the falling edge of the first LP of the frame.
      4  Scan-Doubling Enabled. If set and bit 5 is 0, the scanlines are
         doubled.
      5  AT&T Mode Enabled. If set the AT&T Mode register (3DEh) is enabled.
         If clear the AT&T register is inaccessible.
    6-7  Memory Configuration 0-1.
           0:  3 8Kx8 SRAM or 2 8Kx8 SRAM and 1 8Kx8 ROM.
           1:  1 32Kx8 SRAM
           2:  1 16Kx8 SRAM and 1 8Kx8 SRAM/ROM
           3:  1 32Kx8 SRAM and 1 8Kx8 SRAM/ROM

3D4h index D9h (R/W): AC Control Register                    (CT82c425/6 only)
Bit 0-4  The number of LCD Latch Pulses (-1) for which the AC signal is on
         and off (50% duty cycle)
      7  If set the programmable AC signal is enabled. If clear, the AC signal
         remains ON for one frame and OFF for the next.

3D4h index DAh (R/W): Threshold Register                     (CT82c425/6 only)
Bit 0-3  Threshold Value.
      4  Saturation. If set the shifts in fore- and background colors by
         SMARTMAP is limited to the saturation points, if clear the
         colormapping will be modulo 16
      5  Four Grey Scale Bit. If set 4 grey scales is selected, if clear 8
         grey scales is selected for text modes.
      6  (82c426 only) Alternate Graylevel Algorithm.

3D4h index DBh (R/W): Shift Parameter Register               (CT82c425/6 only)
Bit 0-3  Foreground Shift. The amount of shift for ForeGround colors in the
         text grey scale scheme.
    4-7  Background Shift.

3D4h index DCh (R/W): Horizontal Sync Width Register         (CT82c425/6 only)
Bit 0-7  Number of Dot clocks in the HSYNC pulse.

3D4h index DDh (R/W): Vertical Sync Width Register           (CT82c425/6 only)
Bit 0-3  Vertical Sync Width in scanlines (-1).
    4-7  Blink rate of characters. The character will be on for (value+1)
         frames and off for the same number of frames.
         The cursor blink rate is twice the character blink rate.

3D4h index DEh (R/W): Shift Parameter Register               (CT82c425/6 only)
Bit 0-4  (82c425 only) ECLK. The number of output clock pulses (-1) per pulse
         of the ENABLE CLOCK for the LCD panel
    0-3  (82c426 only) (R) Silicon Revision.
      5  CLK SEL.  0 selects the CLK1 input as the master clock source, 1
         selects the CLK2 input.
    6-7  CCLK DIV 0-1. Determines the panel shift clock (PCLK) and pixel
         clock.
          Value:   Pixel freq:    PCLK (LCD):
            0        CLKIN         CLKIN/4
            1        CLKIN/2       CLKIN/8
            2        CLKIN/3       CLKIN/12
            3        CLKIN/4       CLKIN/16

3D4h index DFh (R/W): Function Control Register              (CT82c425/6 only)
Bit   0  Decode Enable. If clear all accesses to the video memory and the 3Dxh
         registers will be disabled, except for writes to this bit.
         When set the memory and registers are accessible.
      1  Font Enable. If set the font memory can be accessed at B8000h-B9FFFh.
         If clear the font memory is inaccessible.
      2  Font Select. If set the font at B9000h is selected, if clear the font
         at B8000h is the default.
      3  If set the CRT output is selected, if clear the LCD.
      4  (LCD only) Status Control. Controls the behavior of the Display
         Enable bit (3DAh bit 0) and Vertical Sync bit (3DAh bit 3).
         If clear, the Display Enable bit toggles every 16 character clocks,
         and the Vertical Sync bit is active during the first scanline.
         If set the Display Enable bit is active during the first 16 character
         clocks of each scanline, and from row 22 till the end of the panel in
         text modes (row 85 in graphics modes). The Vertical Sync bit is
         active through all scanlines of row 24 in textmodes (row 93 - 96 incl
         in graphics modes).
      5  (LCD only) Enable Control.
      6  If set bit 3 of the attribute byte selects the font, rather than
         intensity.
      7  If set the video outputs are inverted.

3D8h (W): Mode Control register
bit   0  80x25 Alpha mode if set, 40x25 else
      1  Graphics mode if set, alpha else.
      2  BW mode if set, color else
      3  Video Enable. Enable video signal if set
      4  640x200 Graphics mode if set, 320x200 else
      5  if set bit 7 of the attribute controls background, else blink
Note: this register is Read/Write on the CT82c425/6.

3D9h (W): Color Select register
         The function of this register depends on the active mode.
         Text modes:      320x200 modes:         640x200 mode:
Bit   0  Blue border      Blue background        Blue ForeGround
      1  Green border     Green background       Green ForeGround
      2  Red border       Red background         Red ForeGround
      3  Bright border    Bright background      Bright ForeGround
      4  Backgr. color    Alt. intens. colors    Alt. intens colors
      5  No func.         Selects palette
                     Palette 0 is Green, red and brown,
                     Palette 1 is Cyan, magenta and white.
Note: this register is Read/Write on the CT82c425/6.

3DAh (R): Status register
bit   0  Display Enable. If set Horizontal or Vertical Retrace is active and
         the video memory may be accessed by the PC.
      1  Lightpen trigger has occurred if set
      2  Lightpen switch is off if set
      3  Vertical Sync. Vertical retrace active if set.
         Video RAM can be accessed for the next 1.25 ms.
Note: The CT82c425/6 modifies bits 0 and 3 for LCD panels. See 3D4h index DFh.

3DBh (R/W) Clear Light Pen Strobe
Reading or writing this register clears the lightpen strobe. This can happen
before or after the lightpen position is read from 3D4h index 10h-11h.

3DCh (R/W): Set Light Pen Strobe
Reading or writing this register sets the lightpen strobe, causing the
lightpen position to be latched to 3D4h index 10h-11h.
The strobe must be cleared by accessing register 3DBh.

3DDh (W):                                                  (AGA - Plantronics)
bit   4  Set for 320x200 16color mode, clear for all other (16color?) modes
      5  Set for 640x200 4color mode, clear for all other (4color?) modes
      6  If set plane0 is at BC000h-BFFFFh and plane1 at B8000h-BBFFFh,
         if clear plane0 is at B8000h-BBFFFh and plane1 at BC000h-BFFFFh,
      7  Set for 640x200 16color mode, clear for all other (16color?) modes.

3DEh (R/W): AT&T Mode Register                                 (CT82c426 only)
bit   0  AT&T Mode. Only effective if 3D4h index D8h bit 5 is set.
         If clear text modes are displayed as 16line characters and graphics
         modes are displayed 200 line  scandoubled resolution.
         If set text modes are displayed with 16line characters and graphics
         modes are displayed as true 400 line modes.
      3  Page Select. If set display memory is in the 16KB starting from
         BC000h, if clear in the 16KB starting at B8000h. If there is less
         than 32KB of video memory this has no effect.
      6  Enable Underline. If set bit 0 of the attribute byte selects
         underline (as in the MDA), if clear it selects blue ForeGround.
Note: this register is only accessible if 3D4h index D8h bit 5 is set.

3DFh (W):                                                  (AGA - Plantronics)
bit   3  132column monochrome text mode
      4  132column color text mode (3D8h bit 0 must be set)
      5  Set emulation mode in lieu of DIP switch
      6  Set monochrome mode in lieu of DIP switch
      7  Set color mode in lieu of DIP switch


  Video Modes:

  00h T   40  25  2   (8x8)
  01h T   40  25  2   (8x8)
  02h T   80  25  16  (8x8)
  03h T   80  25  16  (8x8)
  04h G  320 200  4
  05h G  320 200  4
  06h G  640 200  2